AMD delivers 128 cores in Bergamo

At AMD’s Data Center and AI Day, the company announced several data center products with which the company is working to further extend its performance leadership across a range of workloads – including cloud, artificial intelligence (AI) and technical computing. In the following sections, I’ll break down the cloud and technical computing announcements. And for the AI-related announcements, check out coverage from Pat Moorhead, CEO and Principal Analyst, Moor Insights & Strategy, here.

First some context

Before we dive into the announcements, let’s set the stage for us to better appreciate what AMD has delivered. In the six years since AMD released the first new-generation server processor (codenamed Naples), the x86 market has undergone significant disruption. First, Intel, the once near-monopoly player, has suffered some execution setbacks, allowing competitive AMD to expand its growing presence among cloud service providers (CSPs).

When AMD started increasing its share of the x86 server market, AWS provided its own home-grown server CPU based on the Arm architecture. AWS not only provided this processor called Graviton, but it did it at scale. This was a pivotal moment for Arm as it showed that architecture can add value in a market full of skeptics. As Graviton became popular, Ampere launched its own Arm-based server CPU called the Altra. Today, every major CSP is deploying Arm-based instances at scale, meeting the needs of customers running containerized cloud-native workloads that thrive on scalable architectures.

Why should CSPs care about deploying ARM in the data center? Doesn’t it increase the complexity of data center operations? The answer: It’s about computational density. While these ARM chips lose most of their low-power advantage when optimized and packaged for servers, you can still pack many CPU cores into a single server. This was true for both Ampere and Graviton. If I need more cores in a server, I can get more processing power per rack unit, which in turn means I can get more customers on a server, lowering my operational costs. Imagine if a CSP bought a 128-core server at a discounted price and then rented each of those cores to customers, there was a lot of money to be made. And if I can lower the cost of my servers, the ROI per core just keeps getting better.

This is why Arm is so attractive to CSPs, and both AMD and Intel view Arm as a serious competitive threat. That’s not just because Arm is taking market share today, but also because — just like Intel supplanted the “Big Iron” in the early ’90s — there’s nothing stopping Arm from working its way up the performance class and breaking the x86 Stealing more and more market share from players. It might be even easier for Arm, since its architecture has strong performance scores compared to x86.

Bergamo – AMD’s cloud chip

Bergamo is AMD’s answer to Arm. This CPU has a core density and power efficiency that rivals Arm.

AMD packed a lot into Bergamo, shrinking the core size (compared to Genoa, the standard 4th Gen AMD EPYC CPU) by 34%. This allows AMD to equip each of its eight computing complexes with 16 cores (compared to eight cores in Genoa). The result is a CPU optimized for performance per watt rather than per core.

These impressive numbers make sense when you consider that “Bergamo” has a 2.1x higher core/thread density ratio than Xeon. I wish AMD had shown a detailed performance comparison with Ampere at their event, with Hyperthreading on and off. Arm specifically designed its Neoverse processor (on which the Ampere Altra is based) as a single-threaded architecture for optimal cloud performance. As such, CSPs have no choice in how to deploy Ampere-based platforms. Will a hyperthreaded x86 part – like the AMD or Intel cloud CPUs coming later this year – deliver a performance-per-watt mark that Amps can’t match?

With that in mind, I like what AMD has done with Bergamo. It’s as much about the company’s attitude to competitive threats in the marketplace as it is about the product itself. The AMD of a few years ago wouldn’t have reacted so strongly.

Genoa-X – 3D V-Cache Enablement for Technical Computing

EPYC’s performance leadership has led to strong adoption in both cloud and high-performance computing (HPC). In the enterprise space, EPYC has also found success in what we might call commercial HPC: technical computing. What is technical computing? Think of product design and performance simulation—the high-performance workloads that engineers, scientists, and others use that require high performance to process large amounts of data. These workloads benefit from powerful cores and large cache blocks. And this is where AMD’s 3D V-Cache comes into play.

Since die sizes are physically limited, it becomes extremely difficult to cram more cache onto the core complex. So instead of building something, AMD built something (hence 3D). This not only allows for more cache, but also a more powerful cache. And the result is dominance from a workload performance perspective.

If you look at the chart above and say, “Not fair – EPYC has a lot more cores,” rest assured that AMD’s performance leadership is still impressive, even with lower-end processors.

Again, I like what AMD is doing. While the company has had less success in the enterprise space than in cloud and HPC, it is attractive for enterprise use cases that have the same performance requirements as the supercomputing clusters that make up the HPC Top 500 list. This continued push could allow AMD to gain a foothold and expand in this stubborn market segment.

Final Thoughts

It’s been a good day for AMD. The company continues to pursue an ambitious plan to further expand data center performance leadership. A step that AMD would not have taken a few years ago. And Bergamo is an excellent response to a competitor not to be taken lightly.

I look forward to seeing how Bergamo compares to Ampere in terms of performance per watt and performance per dollar. And finally, I’m excited for AMD’s CSP launch of the cloud CPU. My gut tells me TSMC will be busy.

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